The present invention relates generally to integrated circuit (IC) design, and, more particularly, to the design of a phase interpolation control for clock and data recovery circuits.
As semiconductor process technology progresses, IC chips can operate at greater speed and offer greater processing power. This places a greater demand for inter chip data communications. High speed serial link communication is one of the most important interface technologies in computers, high-speed routers/switches as well as consumer electronics. During a high speed serial transmission, a data signal is transmitted from a transmission chip. The data signal may be polluted on the transmission line. At a receiving chip, a clock and data recovery (CDR) circuit is provided to recover the transmitted signal. Phase interpolation is often employed in constructing the CDR circuit, which occupies less chip area and consumes less power as compared with phase-locked-loop (PLL) based CDR circuits.
FIG. 1 is a block diagram illustrating a phase interpolation based CDR circuit 100 in a receiving chip. The CDR circuit 100 comprises a pre-amplifier 102, a phase detector 110, a phase interpolation controller 120, a phase interpolation core 130 and an output buffer 140. Incoming data is first amplified by the pre-amplifier 102, and then fed into the phase detector 110 which compares the incoming data with an internally generated clock signal, i.e., INTERPOLATED CLOCK, and produces an EARLY or LATE signal as well as a RE-TIMED CLOCK and a RECOVERED DATA signal through the output buffer 140. The phase interpolation controller 120 responds to the EARLY or LATE signal to generate phase tuning bits to control the phase interpolation by the phase interpolation core 130. The phase tuning bits are typically thermal codes. The phase interpolation core 130 uses the thermal codes to modify the phase of the INTERPOLATED CLOCK signal until the phase of the INTERPOLATED CLOCK aligns with that of the INCOMING DATA. When the INCOMING DATA is ahead of the INTERPOLATED CLOCK, an EARLY pulse will be generated. The EARLY pulse causes the phase of the INTERPOLATED CLOCK to shift ahead and become more in-phase with the INCOMING DATA. On the other hand, if the INCOMING DATA is behind the INTERPOLATED CLOCK, a LATE pulse will be generated. The LATE pulse causes the phase of the INTERPOLATED CLOCK to shift backward and become more in-phase with the INCOMING DATA.
FIG. 2 is a timing diagram illustrating the process of aligning the INTERPOLATED CLOCK signal with the INCOMING DATA signal. The INCOMING DATA and the INTERPOLATED CLOCK have phase differences t1, t2, t3 and t4 at different clock cycles. After each clock cycle, the phase difference becomes smaller, i.e., t1>t2>t3>t4, as a result of the phase interpolation controlled by the phase interpolation controller 120 of FIG. 1.
FIG. 3 is a schematic diagram illustrating a conventional implementation of the phase interpolation core 130 of FIG. 1. Input signals, VCLK-I and VCLK-Q, are clock signals generated by the receiving chip itself. VCLK-I and VCLK-Q has a predetermined phase relationship. An output signal VOUT has a phase interpolated from the phases of VCLK-I and VCLK-Q. The phase of the interpolated output signal VOUT is determined by the magnitude ratio of the current source I1, I2, I3 and I4, which are in turn controlled by the phase tuning bits, or thermal codes, generated by the phase interpolation controller 120 of FIG. 1. Therefore, a function of the phase interpolation controller 120 is to convert the EARLY or LATE signal to a set of corresponding phase tuning bits which cause the phase interpolation core 130 to shift the phase of the INTERPOLATED CLOCK to be more in-phase with the INCOMING DATA. Conventionally, the phase interpolation controller 120 is formed by an analog filter circuit and a thermal code generator. The analog filter circuit is to filter out jitters and noises inherent in the INCOMING DATA signal. However the analog filter circuit typically includes capacitors, the parameters of which fluctuate with different processes. The bandwidth of the analog filter circuit is typically fixed by design. But a chip may be used in different environments with different noise characteristics. The conventional phase interpolation controller 120 with the analog filter circuit may be designed for one application, but may not be ideal for use in another.
As such, what is desired is a phase interpolation controller that is stable and can be dynamically adjusted for use in various applications.